This disclosure concerns methods and apparatus for discerning the logic levels stored in magnetic memory elements as represented by changeable high and low resistance states. For determining the present resistance state of an element, one or more parameters that vary with the resistance of the element are compared against corresponding parameters in a reference circuit.
The reference circuit has one or more reference magnetic memory elements that exemplify both high and low resistance states. The basis of comparison is a level of the parameter falling between parameter levels exemplifying the high and low resistance states, used as a comparison threshold. In one embodiment, an average of current amplitudes through magnetic elements in respective high and low resistance states is compared against a current amplitude in an element to be read out. The result of the comparison denotes whether the element is in a high or low resistance state.
In an embodiment, a same bias current polarity is used for sensing the resistances of the memory element and also the comparison cells, developing voltages that are coupled to the inputs of a voltage comparator. More particularly, the differing fixed or changeable magnetic layers of the high and low resistance comparison cells are arranged in opposite polarity orientations relative to the source of current bias, while the same polarity is used for the source current to both the high and low resistance legs of the reference circuit. This provides a simple and effective circuit for reading out bit values.
The specific current polarity and relative orientation of the magnetic layers are those that avoid risk of read-disturb errors at the comparison cells of the reference circuit, for both the high and low resistance states. However a read-disturb risk remains as to the memory element to be read out, namely if the memory element happens to be in the particular resistance state that is vulnerable to read-disturb errors at the applied current bias polarity. The logic state of the memory element being read out is not initially known, so a read disturb risk is unavoidable at certain combinations of current bias polarity, magnetic element orientation in the circuit, and high or low resistance state.
A spin-transfer torque magneto-resistive random access memory (STT-MRAM) stores data values in storage elements having two superimposed layers of magnetic material separated by a thin insulating film, defining a magnetic tunnel junction or “MTJ”. The two layers include a magnetic layer that is permanently magnetized in a fixed magnetic field alignment direction, and a changeably-magnetized magnetic layer.
The changeably-magnetized magnetic layer can be magnetized in one of two orientations relative to the permanently magnetized layer. The two orientations are characterized by distinctly different serial resistances through the superimposed layers of the MTJ. The magnetic field orientation of the changeable layer can be aligned the same as that of the permanent magnet layer (parallel), or the magnetic field of the changeable layer can be aligned directly opposite to that of the permanent magnet layer (anti-parallel). The parallel alignment state has a relatively lower resistance and the anti-parallel alignment state has a higher resistance. These two states as sensed from their relatively higher or lower resistances (RH and RL) represent different binary logic values of bits in the memory.
The thin insulating layer can comprise magnesium oxide (MgO), for example. The permanent magnet layer is a reference layer and can be termed the “pinned” layer or the pinned magnetic plate. The changeable magnetic layer or plate is termed the “free” layer. When the free layer of a bit cell comprising an MTJ has been magnetized in one alignment direction or the other relative to the field alignment of the reference layer, that condition persists without the need to maintain electrical power to the bit cell. The memory is nonvolatile. A semiconductor memory using MTJ elements can be scaled to a small cell size, requires little power for read and write operations, and functions at frequencies comparable to volatile memory types employing latches or cross coupled inverters, but without comparable levels of current leakage.
For reading the logic value of an MTJ bit cell, a bias current is applied serially through the superimposed magnetic layers, causing a bit cell read voltage to be developed. Assuming that a same bias current amplitude is applied, a voltage amplitude is generated according to Ohm's Law, V=IR, that differs with the serial resistance through the MTJ and superimposed magnetic layers. A higher or lower voltage at the same bias current level indicates whether the bit cell layers are magnetized in their parallel or anti-parallel states.
Using a voltage comparator having a reference voltage level coupled to one comparator input and the bit cell to be read out coupled to the other comparator input, the voltage across the bit cell is compared to the reference voltage and the output of the comparator represents the logic value read out from the bit cell.
An ideal reference voltage level is the voltage that would result from applying the read current to a resistance that is between the high resistance value RH and low resistance value RL and preferably is well spaced from both RH and RL, such as halfway between them. However, manufacturing variations are such that the RH and RL resistances encountered in manufactured MRAM bit cell arrays can vary. Small differences in the thickness of the magnesium oxide or other barrier layer between the magnetic layers can have a particular effect on the resistances RH and RL.
It is possible to provide a voltage comparator coupled to a voltage reference amplitude for each bit cell position in addressable memory words. Switched addressing arrangements are possible for banks of cells, for addressable memory words, etc., in addressed and/or time division multiplexed arrangements. For simplifying this discussion, it can be assumed as a nonlimiting example that plural voltage comparators are provided, one comparator for each bit position of any memory word that is gated or addressed to the comparison circuit. In that example, the bit values for all the bit cells in a memory word are read out in parallel when the bit cells are commonly addressed by a decoded memory word line signal.
The reference voltage applied to the comparators for the bit cells (or for some subset of bit cells such as bit cells at a given bit position) might be determined in various ways. For example, a voltage divider with fixed resistance values between a power supply voltage and ground can define a fixed reference voltage at the junction between the fixed resistances.
One might attempt to define a fixed reference voltage that is slightly below the lowest expected voltage produced by a nominal read-current amplitude through any of the bit cells when in their high resistance state. All bit cell read voltages that produce a read voltage below that may be assumed to be in the low resistance state. Similarly, one could define a reference voltage that is slightly higher the highest expected voltage produced by a nominal read-current amplitude through a bit cell in its low resistance state. All bit cell read voltages that produce a read voltage higher than that may be assumed to be in the high resistance state. These techniques, briefly, use the lowest high resistance or the highest low resistance as the threshold for comparison. Such a configuration would not be optimal because the difference between the comparison threshold and the corresponding memory element value would be small for some of the memory elements being read out. Any offset in the operation of the comparators could produce errors. A better comparison threshold would be well spaced between the lowest high resistance and the highest low resistance.
It may be difficult or impossible to predict a reference voltage that falls at an optimal resistance that is spaced between the lowest high resistance value RH and the highest low resistance value RL of manufactured MRAM circuit chips. A reference value selected appropriately for one chip may be incorrect for another chip. Attempting to use the same reference voltage for chips whose actual RH and RL values are distributed over a statistical population will reduce selections. Some of the chips will have an unduly high proportion of bit cells that cannot be accurately written and read out.
Instead of predicting a fixed reference voltage, a reference voltage can be derived from one or more reference MTJ elements that are manufactured in the same process as the bit cells. If manufacturing variations affect the bit cells (such as variation in the thickness of the magnesium oxide barrier layer) the same variations similarly affect the reference elements. The reference voltage in that case is more accurately optimized for the MTJ elements that are manufactured together. One or more MTJ elements that are known to be in their high resistance state RH and one or more MTJ elements known to be in their low resistance state RL, are biased with a read current and produce voltages from which a reference threshold voltage is derived and coupled to one input of a voltage comparator. The same read current amplitude is applied to a bit cell whose logic value is being read out, and the output of the voltage comparator is the bit cell logic value. What is needed is a simple, dependable and accurate configuration to accomplish this.
When setting the resistance state of an MTJ element that is used in a bit cell, namely when writing a logic value into the bit cell, the required alignment can be imposed onto the free layer, namely by magnetizing the free layer in the necessary direction relative to the pinned layer to define a high resistance (anti-parallel) or low resistance (parallel) alignment state. A spin-transfer torque (STT) cell is advantageous in that the alignment of the magnetic field in the free layer can be changed simply by passing a write current of the required polarity to align the free layer in one direction or the other, and at least a minimum write current amplitude, through the magnetic tunnel junction MTJ element. The polarity needed to change the resistance state from low to high is different from the polarity needed to change from high to low.
When sensing the resistance level of the MTJ element, it is also necessary to apply a current bias for reading purposes. One may avoid inadvertently writing a new alignment state onto an MTJ element (a “read-disturb” error), by keeping the read current amplitude less than the amplitude that might cause realignment of the free layer. A read-disturb error would not be possible if the read current is applied at the polarity that would retain the present alignment of the free layer unchanged in its parallel or anti-parallel state. But the logic value of the bit cell is unknown when commencing a read operation. As a result, the read bias current for bit cells when applying a read current bias is kept low.
In the situation where one provides two or more reference MTJ elements for use as opposite-state resistance references when determining the resistance state (reading out a stored logic value) of a memory MTJ element having a logic state that is unknown, at least one of the reference MTJ elements is necessarily in a different resistance state from the memory MTJ element that is being read out. It seems that in such a case, whether a positive current polarity or a negative current polarity is used to sense the resistance of the MTJ element being read out, there is always a read-disturb risk to the memory MTJ element being read out and also to one of the two elements of the reference circuit. At any read bias current polarity, the memory MTJ element to be read out is at risk if it happens to be in the vulnerable one of its two possible logic states. At any read bias polarity, one of the two reference MTJ elements that are in opposite resistance states is biased in its direction that is vulnerable to read-disturb errors (although the vulnerable one might be the high resistance MTJ or the low resistance MTJ, depending on the direction of current bias). It seems impossible to resolve the possible current bias possibilities to the reference circuit and also to the MTJ element to be read out, in a manner that does not risk a read-disturb error to the memory MTJ element and one of the two reference MTJ elements. What is needed is to manage the risk of read disturb errors as well as to optimize the configuration of the MTJ elements in the reference section coupled to a sense amplifier in an STT-MRAM memory circuit.